I’m an ASIC Verification Engineer with over 2.5 years of experience in UVM-based and formal verification. I’ve worked on Ethernet Switch IPs at Rockwell Automation, building reusable testbenches, achieving full coverage, and automating regressions. Passionate about SystemVerilog, UVM, and protocol-level validation (AXI, APB, Ethernet), I love helping others strengthen their verification concepts and interview readiness through practical, real-world insights