Testimonials
Lalith explained a complex topic like driver upsizing and aggressor-victim crosstalk in such a clear and concise manner. His response helped me understand not just the "what" but the "why" behind upsizing/down-sizing decisions in physical design. Appreciate his practical insight and the emphasis on careful what-if analysis. Lalith has been incredibly helpful with multiple queries I’ve asked him. He always explains things clearly and to the point, no matter how complex the topic is.He’s a person with strong subject knowledge and a genuine intent to help learners. I truly appreciate his support and highly recommend him to anyone seeking VLSI guidance!
I recently had a quick chat with Lalit about a doubt I was having on a STA topic, and I have to say, he explained everything so clearly! He made a complex concept much easier to understand, and I really appreciated how patient and thorough he was. Lalit’s ability to break things down and ensure I was following along made a huge difference. Definitely recommend reaching out to him if you’re looking for help with tricky topics!
Had a few discussion with Lalit regarding STA and EMIR related queries. Found him to be very knowledgeable and clarifies even every minute details regarding the concepts. Would like to recommend others also for clarifying any STA/EMIR related concepts.
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About me
✓ Accomplished Lead Full Chip Timing Engineer with ~7 years of industry experience.
✓ Expertise in STA, constraints management, ECO generation, and global architectures (TAP/SSN/MBIST).
✓ Skilled in PDN simulations, performing IR-aware timing analysis, and proficient in physical design.
✓ Focused on integration and timing closure of 3D IC systems.
✓ Innovating new methodologies to improve modeling & signoff processes.
✓ Proficient with tools like Primetime, Tempus, Tweaker, Fishtail, Redhawk, and Spice; moderately skilled in Fusion Compiler and Innovus.