I am an accomplished ASIC Design Engineer with extensive experience in silicon design, verification, and hardware architecture. Currently working at Microsoft IDC as a Silicon Design Engineer, specializing in maintaining and enhancing Global Libraries, collaborating with cross-functional teams to enable early-stage synthesis and verification across multiple process technology nodes. I have a strong background in assertion-based verification, CI/CD pipeline support, and RTL feature development. Previously, I held roles at Qualcomm and Western Digital, where they contributed to DFT architecture implementation, power-aware scan partitioning, and post-silicon bring-up. My technical expertise spans Verilog, System Verilog, C/C++, and scripting languages, with hands-on experience in industry-standard tools such as Cadence, Synopsys, Siemens Tessent, and Azure DevOps. I hold an M.Tech in VLSI & Embedded Systems from IIIT Delhi and a B.Tech in Electronics from Maharaja Agrasen Institute of Technology. Notable projects include ARM Cortex M0 core implementation, complete VLSI design flow execution, and innovative work on digital hardware modules and arcade game development. My process node experience ranges from 4nm to 180nm, demonstrating versatility and depth in semiconductor design.