4+ year experience in VLSI Industry -Technology nodes: 4nm , 5nm and 16nm -Worked in Static Timing Analysis which include analyzing setup, hold, transition, crosstalk, min period/pulse & noise violations. Analyzing detours and region location for instances in clock path to resolve clock skew issues. -Also worked on Tweaker ,Tempus ECO, Leakage Recovery ECO and Primetime ECO for fixing setup, hold and data transition issues. -Prepared manual ECO for hold fixing and TDRC fixing. - CID and ETM generation, clockQOR generation - HM to SOC correlation,sanity checks, spef generation using Quantus - Clock push/pull -Designed floorplans - Solving congestion issues - DRC ,LVS ,MRC - constraints augmentation - GCA -EDA capability: Innovus ,Fusion Compiler ,Primetime ,Tempus ,Tweaker ECO , Calibre , IC Validator , StarRC , Power Wizz , Ostrich RC correlation