anuj panwar

Over the last few sessions and follow-ups, several students specifically requested a structured RTL-focused program, which is why I’m opening the first RTL Design live cohort

This will be a 12-week structured program, limited to 25 participants, designed for students who want to learn how RTL is actually written, reviewed, and reasoned about in industry.

Focus areas

1. Writing clean, review-ready RTL (SystemVerilog)
2. Core building blocks: FIFOs, arbiters, ready/valid protocols
3. RTL design thinking and micro-architecture basics
4. How RTL interfaces with DV and PD in real chip teams
5. Guided problem-solving and design exercises (not recorded theory)