About me

I am an experienced professional in VLSI design and semiconductor engineering, holding a Master’s degree in Electrical Engineering from the University of Southern California. Currently, I work at NVIDIA, where I contribute to cutting-edge ASIC and RTL design projects. My expertise includes digital design, high-performance computing, and hardware description languages like Verilog and SystemVerilog. I have a strong track record in optimizing power, performance, and area (PPA) for complex chips. In addition, I have developed custom circuits for intricate designs and worked extensively on physical design, including floor planning, routing, and clock distribution. I have experience collaborating with cross-functional teams to deliver innovative silicon solutions. I am skilled in microarchitecture (uArch), power analysis, debugging, synthesis, and timing analysis. Passionate about advancing hardware acceleration and AI-driven chip design, I am committed to pushing the limits of semiconductor technology.