- Anuj Panwar excels in mentorship, providing valuable insights and guidance in VLSI. His impactful mock interviews and supportive nature enhance mentees' confidence and skills.
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Services
Video meeting . 10 mins
4.9
RTL Design Cohort Shortlisting
Video meeting . 30 mins
Resume Review
Resume review for VLSI & hardware design roles
RTL Mock Interview . 45 mins
5
RTL Design Mock Interview
Industry-style RTL mock interview with detailed feedback
Video meeting . 30 mins
5
Master’s Degree Mentorship
Gain expert guidance on applying for a Master’s in EE
Package . 5 products
Hardware Interview Accelerator (RTL)
Complete interview prep for RTL & hardware design roles
Resume Review
Video Meeting
1
Career in VLSI/Hardware design
Video Meeting
1
RTL Design Mock Interview
RTL Mock Interview
3
Priority DM . 2 days reply
RTL Design Cohort – Shortlisting
Shortlisting for RTL course
Video meeting . 30 mins
5
Career in VLSI/Hardware design
Unlock your potential in VLSI and hardware design
Video meeting . 45 mins
5
Custom Circuit Design Mock Interview
Circuit design mock interview with detailed feedback
Package . 5 products
Hardware Interview Accelerator (Circuit Design)
Resume Review
Video Meeting
1
Career in VLSI/Hardware design
Video Meeting
1
Custom Circuit Design Mock Interview
Video Meeting
3
About me
I am an experienced professional in VLSI design and semiconductor engineering, holding a Master’s degree in Electrical Engineering from the University of Southern California. Currently, I work at NVIDIA, where I contribute to cutting-edge ASIC and RTL design projects. My expertise includes digital design, high-performance computing, and hardware description languages like Verilog and SystemVerilog. I have a strong track record in optimizing power, performance, and area (PPA) for complex chips. In addition, I have developed custom circuits for intricate designs and worked extensively on physical design, including floor planning, routing, and clock distribution. I have experience collaborating with cross-functional teams to deliver innovative silicon solutions. I am skilled in microarchitecture (uArch), power analysis, debugging, synthesis, and timing analysis. Passionate about advancing hardware acceleration and AI-driven chip design, I am committed to pushing the limits of semiconductor technology.