✅ Experienced in Design Verification at SoC/IP level with strong expertise in SystemVerilog and UVM methodology. Proven ability to build self-checking simulation environments from scratch for SoCs, ASICs, and FPGAs, ensuring comprehensive functional coverage. ✅ Hands-on experience with memory protocols like DDR5 and LPDDR5, with a focus on functional verification and integration aspects. ✅ Working knowledge of inline ECC (Error Correction Code) techniques for memory data integrity verification, ensuring robustness in high-performance designs. ✅ Good understanding of standard bus and interconnect protocols including AXI, APB, AHB, with basic knowledge of CHI protocol, especially in multi-core and cache-coherent system environments. ✅ Proficient in developing UVM-based testbenches from scratch, including sequences, scoreboards, monitors, and coverage components. Strong debugging skills, including GLS (Gate-Level Simulation) for corner-case validation. ✅ Knowledge of assertion-based verification using SystemVerilog Assertions (SVA) to enforce protocol and functional correctness. ✅ Skilled in scripting with Python and PERL for automating regressions, testbench utilities, and log analysis. ✅ Comfortable with industry-standard tools like VCS, Irun, VManager, VPlanner, IMC, and collaboration tools like Jira and Confluence. ✅ Excellent communication and interpersonal skills, with the ability to learn new concepts quickly and apply them effectively in complex verification environments.