DFT interview questions for all experience levels

This video series contains four parts that answers the below questions:

General DFT:

1) Why DFT needs to be done / what is the purpose of DFT? **

2) What is DPPM/Yield - What is your DPPM?

3) What is the advantage/disadvantage of DFT?

4) Where in ASIC/Chip design flow, DFT comes into picture?

ATPG:

1) Why transition coverage is low compared with stuck at? what is the difference betweenn stuck at and transition model? **

2)Do not NEED Coverage on Resets, SE pins of Flop.

3)We Do not cover cross-clock (Asynchronous logic) in Transition.

4) We Do not cover False Paths, MCPs.

1b) on silicon what manufacturing issue will lead to stuck at defect / transition defect ?

2) I have a transition pattern set that has 95% coverage. How much stuck at coverage I will get

Transition

3) what are different ways of at speed pattern generation?

4) what are advantages/disadvantages of LOC/LOS? *

5) what is the purpose of OCC? ***

6) Explain the structure of OCC?

7) Is it possible to get more than two pulses? Max how many we can get? How to

8) what is fast sequential ATPG?

9) what is sequential depth in ATPG?

10) What is the ATPG flow from tool point of view?

11) what is there in spf(tetramax) /test_protocol file (tessent)

12) what is a CTL model and where it is used?

13) what are the different fault classifications in ATPG?

14) what is the process you will follow for coverage analysis? ****

15) My ATPG coverage is too low (like 18-20 %). What is the first thing you will check?

16) what is the concept of SCAN INTEST/EXTEST ? ***

17) Explain the SE status of input wrapper/output wrapper cell in both EXTEST/INTEST? ****

18) My ATPG coverage is 94% - How will you proceed? (Target is 99.5% )

19) My ATPG coverage is 98% - How will you proceed? (Target is 99.5% )

20) My ATPG coverage is 99.4% - How will you proceed? (Target is 99.5% )

21) Is it possible to get 100% coverage?

22) what is the status (of clock, reset) of core flop when you are doing SCAN EXTEST? **

23) when we add dummy cycles in ATPG w.r.t LOC?

24) what are false path and multicycle path and how stuck at/transition coverage is affected?

25) what is the abort limit?

26) why shift frequency is low? what is the shift frequency you used ? what happens if the shift

frequency is too high ?

27) what is the functional frequency or at speed frequency?

28) Explain one scenario where you increase coverage?

29) common causes of scan chain blockage? How to fix it? (some clocks /reset is not declared in

ATPG tool / programming issue) **

30) common DRC violations *****

31) you ran ATPG,what all will you check ?

32) why scan compression is needed ?

33) what are the Advantages and disadvantages of compression ?

34) How do you decide on the compression ratio ? What analysis you will do ?

35) what is difference between serial and parallel pattern simulation? Are both needed? can we

36) parallel pattern simulation is passing / Serial failing - What could be the issue?

37) serial pattern simulation is passing / parallel failing - What could be the issue?

38) what is your approach to simulation debug? *

39) Given a block with small size (say 8k flops) , on what factors you decide compression or not

40) why to do timing-based simulations?

41) what issues you saw in timing / no timing simulations - simulation fail scenarios?

42) why to do notiming based simulations ?

43) what are the inputs needed for scan insertion ?

44) what are the inputs needed for ATPG ? Delivery to other teams ? **

45) what is SDF file ? What is inside it ? *

46) what is SDC file ? what does it contain ?

47) what is pattern retargetting in ATPG ?

48) what is fault aliasing ?

49)A chip on silicon has always shift output 0 i.e..,some flops Q is stuck to 0. How will you figure

out?

50)why to do netlist sim [gate level sim ] ?

51)How you do low power ATPG pattern generation ?

52)How many corners you do timing simulation?

53)How many scan clocks you have in your block?

54) What are the fault models other than stuck at, transition?

observed on path with minimum slack .

BSCAN/JTAG/IJTAG:

1) why boundary scan (1149.1) came into picture? what is the primary usage of boundary scan

? *

Ans--> BSCAN is used for board level testing - to test the interconnect between two chips

2) what is difference between JTAG/IJTAG ?

Time.

3) what are mandatory instructions in JTAG ?

4) what are the pins in JTAG ?

5) How many states in JTAG FSM ?

6) How to reset the tap without TRST (How to do sync rest of the TAP ?)

7) How to do JTAG EXTEST ? Explain

8) How to do JTAG INTEST ? Explain

9) Explain the basic structure of boundary scan cell and modes in it ? ****

10) what is the purpose of IEEE 1500 ?

11)What is the instruction code for bypass ?

12)what is length of Instrution register ?

13)what is the instruction code for EXTEST ?

14)what is the default instruction for jtag ?

15)There are 10 chips on the board .How do you select the 3rd chip in them ?

16)In BYPASS mode,why do we need a flop between TDI--> TDO path ? we can directly connect

TDI to TDO right?

MBIST:

1) What are the fault models in MBIST?

2) on what factors you group memories in a controller ? *

3) what algorithms are used in MBIST ?

4) what inputs are needed to do MBIST ?

5) what are the outputs of MBIST ?

LOCKUP LATCH*:

1) Why lock up latch is needed or what is the purpose of lockup latch ? **

2) which path we are adding lockup latch ?

3) If +ve flop,-ve flop order (same clock/different clock ) do we need lock up latch and why ?

4) If -ve flop,+ve flop order (same clock/different clock ) do we need lock up latch and why ?

5) Can we use lock up flop instead of lockup latch?

6) if clock skew > 1/2 cycle,will lockup latch work ?

7) if skew > 1/2 cycle,what is the solution ?

8)what is the disadvantage of lockup latch?

9)why is lockup latch needed at the end of every short chain in bypass mode?