1. As a Senior Physical Design Engineer at MosChip, I work on deep submicron technology nodes, from Place and Route (PnR) to GDSII, with a focus on low power design and sign off timing closure. I have successfully completed two tapeouts and fixed multiple issues related to physical verification, IR drop, and cross talk. I am also a graduate student in Electrical and Electronics Engineering at Portland State University, where I am learning advanced topics in physical design, such as clock tree synthesis, power integrity, and design for testability. My goal is to enhance my skills and knowledge in this domain and contribute to the innovation and quality of the semiconductor chip design industry.