Highly Skilled Analog & Mixed-Signal Layout Engineer with extensive experience in designing and delivering high-performance, high-speed analog and mixed-signal IPs across advanced semiconductor technologies. Proven expertise in end-to-end ownership of layout development from schematic to GDS, including full-chip integration and sign-off. Specialized in DDR, PHY, PMIC, BGR, LDO, IO, Clocking circuit architecture, and high-speed analog circuits, with deep hands-on experience across multiple nodes. Demonstrated ability to independently drive complex projects, including single-handed execution of full-chip and IP-level designs, ensuring high quality and on-time tape-out. Strong background in full-chip physical verification (LVS, DRC, EM/IR, antenna) and layout optimization techniques addressing matching, latch-up, EMIR, antenna effects, density compliance, and second-order effects. Extensive exposure to advanced and mature technology nodes including TSMC (N2, N3, 14nm, 16nm, 28nm, 45nm, 90nm, 180nm), Intel (18A, 14A, Intel 3, 7nm, 10nm), GlobalFoundries (180nm), STMicroelectronics (28nm, 14nm), and Avago (600nm). Proven expertise in ESD, Pad/Bump planning and Full chip integration for internal and external customer. Recognized with multiple DIA, DRA, and PRA awards at Intel for technical excellence and execution. Proven ability to manage multiple high-priority projects simultaneously, while driving layout methodologies, IP integration strategies, and documentation at IP and SoC levels. Experienced in team handling and technical leadership, with a strong ability to collaborate across cross-functional and geographically distributed teams. Proven track record of driving end-to-end execution of complex chip development programs, ensuring alignment across domains and successful on-time delivery. Skilled in managing multi-time-zone interactions, resolving dependencies, and maintaining high standards of quality and execution. Various paper presentation including multiple IEEE paper author.