Hi! I'm a seasoned ASIC RTL Design Engineer with over 10 years of hands-on experience in the semiconductor industry. My core expertise lies in Digital IP Design, focusing on SystemVerilog-based RTL coding, CDC (Clock Domain Crossing) analysis, Lint checks, Low-Power architecture (UPF/CPF), and synthesis-aware design practices. I’ve contributed to multiple successful ASIC tape-outs, working across IP-level to SoC integration. Over the years, I've mentored engineers, interns, and VLSI enthusiasts, helping them bridge the gap between theory and industry-level design expectations. 🔧 Areas I Can Help You With: RTL Design Best Practices using SystemVerilog CDC and Lint Issue Debugging & Methodologies Low-Power Design Techniques (UPF, Power Aware Simulation) Writing Synthesis-Friendly RTL Design Review & Optimization Guidance Building a Career in VLSI/ASIC Industry Resume and Interview Preparation (Front-End Design roles) Whether you're a student, a junior engineer, or someone looking to switch into RTL/ASIC roles, I offer personalized 1-on-1 sessions to help you build confidence and clarity in your digital design journey. Let’s work together to take your skills to the next level!