Results-oriented senior technical leader with a proven track record of success in working with C-level leadership roles. Recognized as a thought leader in high tech semiconductor industry with deep expertise across semiconductor value chain from EDAaaS, capital equipment vendor interaction, materials suppliers, packaging/OSAT, fab digital transformation, supply chain resiliency, to ecosystem creation leveraging strategic partnerships, semiconductor technology inflection trends such as chiplet architectures, Nanosheets, and stacked FETs. Passionate about driving innovation, leading large high-performing teams, and delivering exceptional results. Skilled in strategic planning, business development, and fostering cross-functional collaboration. Committed to sharing insights and thought leadership to inspire industry professionals and drive positive change. Currently, I run Strategy and Growth Partnerships at IBM Semiconductors, a business in IBM Research. Prior to that(2018-2022), I led a large team of semiconductor technologists to execute yield step up plans for Pathfinding logic technologies such as 5nm Nanosheets , <3nm Stacked FET, BSPDN); and Analog compute memory architectures. These were first-of-a-kind yield learning programs to run in Albany at scale. To accomplish this, I focus on KPIs, leverage technical leadership in multiple Yield learning JDAs, and quickly adapt to change, new insights. Roles and Responsibilities: 1. Manager of Global Defect Inspection and Advanced Failure Analysis Org with engineers from IBM, Samsung, Global partners. 2. Technical lead for two client engagements(~10M) with Net Promotor Score 9. 3. Technical lead for GAA- Nanosheets yield demonstration. 3. Technical lead for Heterogenous Integration(HI) and Chiplet Inspection/Metrology strategy. Prior to my managerial role(2015-2018), I was the lead in process development group for 10nm, 7nm Etch and Ion Implants. Evaluated Best-of-Breed tool installation, and process qualification for Advanced Logic and Memory(SRAM, MRAM, PCM) technologies. Transferred Co as interconnect material for 10/7nm Finfet technology enablement to foundry partner. I have a Phd in Material science from University at Albany and M.S. in Electrical Engineering from Michigan Tech. I enjoy learning about new technologies and commit to learn new skills that would complement my leadership role. --The postings on this site are my own and don't necessarily represent Accenture’s positions, strategies or opinions--