👋 Hi, I’m Abhishek. I help aspiring and working engineers understand Design Verification, present their skills clearly and prepare for their next career step. Whether you’re exploring your first VLSI role, switching into DV or preparing for a new opportunity, we’ll start with your background, your questions and what you want to achieve. 🔬 Industry experience that connects theory to practice My experience includes multiple tap-outs of Intel legacy Xeon Servers as part of IP level verification. I am well versed with the entire end to end flow for a complex industry standard IP level verification and fully acquainted with entire verification methodology. I’ve worked across - 1. Verification planning 2. UVM test-bench architecture 3. Assertion development 4. Constrained-random and directed testing 5. RTL debugging and 6. Coverage closure Collaborating closely with designers to investigate failures and verify intended behaviour. I bring that engineering perspective into our sessions: how to approach a problem, reason through your choices and explain your work with clarity. I have keen interest in Digital design architecture and microarchitecture, verification test bench architecture and ASIC verification flow. I am always keen on learning new skills and honing them for continuous growth and learning. 🎯 How I can help you • DV Doubt Session — Work through one focused question in SystemVerilog, UVM, assertions, coverage or debugging. • DV Career Roadmap — Identify your learning priorities, relevant project work and practical next steps. • Resume + LinkedIn Review — Make your skills, project contributions and engineering decisions easier for recruiters and interviewers to understand. • DV/UVM Mock Interview — Practise technical reasoning and communication, then get specific feedback on your strengths and improvement areas. • Personalised DV Mentorship — Take a deeper look at your skills, projects and preparation, and turn your priorities into an actionable plan. 🤝 What you can expect from me Space to ask foundational questions without hesitation. Patient explanations. Honest, constructive feedback. Guidance shaped around your starting point. My experience interviewing engineering candidates helps me coach both what you know and how you communicate it. Each service includes its stated written takeaways and follow-up support, so you have something concrete to work on after the conversation. 🛠️ My technical toolkit 1. Verilog 2. System Verilog 3. UVM 4. SVA 5. Functional and code coverage Protocol experience: APB, AHB and SPI Tools: Synopsys VCS/DVE, Cadence SimVision and QuestaSim Education: M.Tech, IIT Delhi ✨ Bring your question, your resume or your next career goal. Choose a session below, and let’s work out your next step together.