I have total 8+ years of experience in FPGA based projects worked in multiple domains like designing Algorithms on Matlab & Simulink, Translating same to RTL/IP based designs in VIVADO. Testing same on HW. At AMD, I have advanced with the Versal premium devices, focusing on TCP of load engine design and verification. my contributions in IP integration in the SoC has been pivotal in enhancing IP-based design, validation, and board bring up for state-of-the-art semiconductor technologies. At Mavenir Systems, I've successfully delivered robust LTE PHY layers and leveraged my expertise in MATLAB, Simulink, and Xilinx Vivado to develop precise digital signal processing algorithms. With a Master's in Digital Electronics and Communication, the foundation from MVJ College of Engineering has been instrumental in my success.