Lead CPU Design Engineer at Qualcomm, working on digital signal processor (DSP) design across various cores and tiers. Graduated from Delhi Technological University (B.Tech, ECE) as both the Vice-Chancellor’s and Chancellor’s Gold Medalist, with 3 published research papers. Started the professional journey in SoC Design Verification at Qualcomm, contributing to IoT, Server, and Compute platforms for 4 years before pursuing a master’s in electrical & computer engineering at University of Texas at Austin, graduating with a 4.0 GPA. Post-Master’s, transitioned into CPU RTL Design in Austin, TX, and later moved to the Bangalore CPU (DSP design) team. Core Areas: CPU RTL Design | Computer Architecture | Microarchitecture | SoC Design & Verification | Timing, Area & Power Optimization | UVM Languages & Tools: System Verilog | Verilog | C | Python | Perl | Synopsys Verdi, VCS How I Can Help: - MS admissions strategy (university shortlisting, SOP/LOR review, GRE 322 & TOEFL 117 preparations, TA/RA funding guidance). I was able to get admits from Michigan, CMU, UW Madison, Texas A&M, UCSD, USC and few others. - Breaking into Core VLSI / RTL / CPU Design roles - Switching domains from Verification → Design - Resume and interview prep for top semiconductor companies - Selection of B.Tech colleges/universities in India based on competitive exam scores and desired field of study - Guidance on navigating B.Tech and how to publish research papers that can boost your masters' application.