About me

- blogger : https://physical-design-asic.blogspot.com - With 12+ years of experience in Physical design engineering, working in Well- Known Product based company, currently leading a team and oversee various aspects of the design process from RTL to GDS. - worked on complex block level designs at multiple nodes, including 90 nm, 28 nm, 16 nm, 7 nm, 6 nm, 5 nm, and 3 nm. - With my extensive experience in FullChip STA closure, I also excel in FullChip STA activity including check timing, quality of constraints validation, and coverage analysis, timing closure. - Hands-on experience with physical design flow, RTL to GDS flow including Physical Synthesis , floorplan, power planning, placement, clock tree synthesis, routing, and signoff, as well as EM-IR analysis. - Tool expertise : Synopsys --> ICC/ICC2/FC/PTSI/PTPX/PrimeRail, Ansys -> Redhawk,Redhawk_sc Cadence --> SOC Encounter/Innovus, Magma --> Talus - strong scripting capabilities in shell/Perl & TCL/TK. - Proficiency in utilizing industry-leading tools such as Synpsys --> ICC/ICC2/PTSI/PTPX/PrimeRail , Ansys --> Redhawk/Redhawk_sc, , SOC Encounter/Innovus -Cadence, and Talus - Magma, sets me apart from my peers and showcases my ability to work with a diverse range of software platforms.