I am a highly skilled Design Verification Engineer with 6+ years of experience in functional verification of complex SoCs and IPs. Key Skills & Expertise - Verification Methodologies: UVM, Constrained Random Verification, Test Planning & Execution, Regression Testing, Coverage Driven Verification, Functional Coverage Analysis, Assertion-Based Verification (SVA). Tools & Technologies: Cadence Xcelium, JasperGold, IMC, vManager, SystemVerilog, Verilog, C/C++, Python, Gate Level Simulation. Protocols: SPI, I2C, AXI4, PCIe (Physical Layer), Basics of CXL.